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[SCMVHDL范例

Description: 最高优先级编码器 8位相等比较器 三人表决器(三种不同的描述方式) 加法器描述 8位总线收发器:74245 (注2) 地址译码(for m68008) 多路选择器(使用select语句) LED七段译码 多路选择器(使用if-else语句) 双2-4译码器:74139 多路选择器(使用when-else语句) 二进制到BCD码转换 多路选择器 (使用case语句) 二进制到格雷码转换 双向总线(注2) 汉明纠错吗译码器 三态总线(注2) 汉明纠错吗编码器 解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog一些译码器源代码

Description: 内有LED译码器,汉明纠错译码器,地址译码器,最高优先译码器,双2-4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code
Platform: | Size: 4096 | Author: 蔡孟颖 | Hits:

[matlabhammingcoding

Description: 信道编码线性分组码hamming码的编码器译码器设计与仿真实现。-channel coding linear block code hamming yards Encoder Decoder Design and Simulation.
Platform: | Size: 39936 | Author: yx | Hits:

[matlabdecode

Description: 解码器,利用差错控制算法解汉明码,BCH码等多种码字-Decoder, error control algorithm using Hamming Code, BCH Code and other code words
Platform: | Size: 2048 | Author: 傲然寒风 | Hits:

[VHDL-FPGA-VerilogHammingEncoder

Description: VHDL编写的汉明纠错码译码器,数字传输中汉明纠错码的译码所用-VHDL prepared Hamming error-correcting code decoder, digital transmission Hamming error-correcting codes used in the decoding
Platform: | Size: 1024 | Author: wei | Hits:

[VHDL-FPGA-VerilogVHDL

Description: VHDL程序集锦,很多有用程序,英文版其中有汉明码编译码,优先译码等等。-VHDL Collection procedures, many useful procedures, the English version of them hamming code encoding and decoding, the priority decoder and so on.
Platform: | Size: 168960 | Author: 萍果 | Hits:

[VHDL-FPGA-Veriloghanmingjiaozhi

Description: 通过VHDL实现汉明码,交织码的编码与解码,开发环境Quartus-Through VHDL realize hamming code, interleaving the encoding and decoding code, development environment, Quartus
Platform: | Size: 3072 | Author: mayue | Hits:

[VHDL-FPGA-VeriloghammingDec

Description: hamming/汉明码的解码代码,在通信中常常用到汉明码-hamming/hamming code decoder code, usually used in communication Hamming Code
Platform: | Size: 1024 | Author: leng | Hits:

[source in ebookHammingDecoder

Description: -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY hamdec IS PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4 dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3 sec, ded, ne : OUT BIT) --diagnostic outputs END hamdec ARCHITECTURE ver1 OF hamdec IS BEGIN --- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY hamdec IS PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4 dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3 sec, ded, ne : OUT BIT) --diagnostic outputs END hamdec ARCHITECTURE ver1 OF hamdec IS BEGIN
Platform: | Size: 4096 | Author: djs | Hits:

[ARM-PowerPC-ColdFire-MIPSma_CRC_files

Description: decoder of Hamming Use a [7,4] Hamming code. m = 3 n = 2^m-1 k = n-m parmat = hammgen(m) Produce parity-check matrix. trt = syndtable(parmat) Produce decoding table. recd = [1 0 0 1 1 1 1] Suppose this is the received vector. syndrome = rem(recd * parmat ,2) syndrome_de = bi2de(syndrome, left-msb ) Convert to decimal.-decoder of Hamming Use a [7,4] Hamming code. m = 3 n = 2^m-1 k = n-m parmat = hammgen(m) Produce parity-check matrix. trt = syndtable(parmat) Produce decoding table. recd = [1 0 0 1 1 1 1] Suppose this is the received vector. syndrome = rem(recd* parmat ,2) syndrome_de = bi2de(syndrome, left-msb ) Convert to decimal.
Platform: | Size: 69632 | Author: le thanh tan | Hits:

[matlabDecoder

Description: 通用汉明码译码器,并加入容错处理,MATLAB源程序-General Hamming code decoder, and add fault tolerance, MATLAB source code
Platform: | Size: 2048 | Author: michael | Hits:

[Communication-Mobilehamming_decoder

Description: VHDL编写的Hamming码的程序,可以正确解码--- This Hamming decoder accepts an 8-bit Hamming code and performs single error correction and double error detection.
Platform: | Size: 1024 | Author: 郑全 | Hits:

[VHDL-FPGA-Verilog74-Hamming-code-encoder-and-decoder

Description: 基于VHDL实现(7,4)汉明码的编码器和译码器-VHDL-based implementation (7,4) Hamming code encoder and decoder
Platform: | Size: 3072 | Author: 付沅键 | Hits:

[VHDL-FPGA-VerilogHamming

Description: 7bit Hamming code decoder, error detection and correction
Platform: | Size: 4096 | Author: Alessandro | Hits:

[Communicationcyclic

Description: script for simulating BER with Cyclic Hamming Code (7,4) with G=1+X+X^3 and Meggitt decoder
Platform: | Size: 1024 | Author: mahdi | Hits:

[Software EngineeringHamming-code

Description: Hamming code encoder and decoder for (11,7,1)format
Platform: | Size: 444416 | Author: Bheemaraj | Hits:

[assembly languageproject.tar

Description: In this assignment you will be designing a chip that both encodes and decodes a data stream using a Hamming code. You will also inject random errors into the data stream and your decoder must be able to fix single-bit errors. Note: This project is intended to be individually. I don’t have a problem if you wish to discuss the project with other students however your final work must be your own. 2. Functional Specification The chip has to implement the following functions: a) Encode a byte of data using 4-parity bits using a Hamming function b) Decode data using Hamming function, perform error correction -In this assignment you will be designing a chip that both encodes and decodes a data stream using a Hamming code. You will also inject random errors into the data stream and your decoder must be able to fix single-bit errors. Note: This project is intended to be individually. I don’t have a problem if you wish to discuss the project with other students however your final work must be your own. 2. Functional Specification The chip has to implement the following functions: a) Encode a byte of data using 4-parity bits using a Hamming function b) Decode data using Hamming function, perform error correction
Platform: | Size: 1024 | Author: Amalathithan | Hits:

[VHDL-FPGA-VerilogError-Correcting-For-7bit-Hamming-Code

Description: Verilog Module for a 3 to 8 bit decoder
Platform: | Size: 84992 | Author: Raz | Hits:

[Picture Viewer04688109

Description: 信道编码线性分组码hamming码的编码器译码器设计与仿真实现-Channel coding of linear block code hamming code encoder decoder design and simulation implementation,,
Platform: | Size: 39936 | Author: pkwordrr | Hits:

[Special Effects8983847

Description: 信道编码线性分组码hamming码的编码器译码器设计与仿真实现,,(Channel coding of linear block code hamming code encoder decoder design and simulation implementation,,)
Platform: | Size: 39936 | Author: Axvin | Hits:
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